5.2 Exception Processing Registers

Cache Error (CacheErr) Register (27)

The 32-bit read-only CacheErr register processes ECC errors in the secondary cache and parity errors in the primary cache. Parity errors cannot be corrected.

All single- and double-bit ECC errors in the secondary cache tag and data are detected; single-bit errors in the cache tag are automatically corrected. Single-bit ECC errors in the secondary cache data are not automatically corrected.

The CacheErr register holds cache index and status bits that indicate the source and nature of the error; it is loaded when a Cache Error exception is asserted.

Figure 5-12 shows the format of the CacheErr register and Table 5-10 describes the CacheErr register fields.



Figure 5-12 CacheErr Register Format

Table 5-10 CacheErr Register Fields

Table 5-10 (cont.) CacheErr Register Fields

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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