Error Checking and Correcting (ECC) register reads or writes either secondary-cache data ECC bits or primary-cache data parity bits for cache initialization, cache diagnostics, or cache error processing. (Tag ECC and parity are loaded from and stored to the TagLo register.)
The ECC register is loaded by the Index Load Tag CACHE operation. Content of the ECC register is:
- written into the primary data cache on store instructions (instead of the computed parity) when the CE bit of the Status register is set
- substituted for the computed instruction parity for the CACHE operation Fill
- XORed into the secondary cache computed ECC for the following primary data cache CACHE operations: Index Write Back Invalidate, Hit Write Back, and Hit Write Back Invalidate.
