-Status Register (12)

5.2 Exception Processing Registers

Status Register (12)

The Status register (SR) is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the processor. The following list describes the more important Status register fields; Figures 5-5 and 5-6 show the format of the entire register, including descriptions of the fields. Some of the important fields include:

The 8-bit Interrupt Mask (IM) field controls the enabling of eight interrupt conditions. Interrupts must be enabled before they can be asserted, and the corresponding bits are set in both the Interrupt Mask field of the Status register and the Interrupt Pending field of the Cause register. For more information, refer to the Interrupt Pending (IP) field of the Cause register and Chapter 15, which describes the interrupts.
The 4-bit Coprocessor Usability (CU) field controls the usability of 4 possible coprocessors. Regardless of the CU0 bit setting, CP0 is always usable in Kernel mode.
The 9-bit Diagnostic Status (DS) field is used for self-testing, and checks the cache and virtual memory system.
The Reverse-Endian (RE) bit, bit 25, reverses the endianness of the machine. The processor can be configured as either little-endian or big-endian at system reset; reverse-endian selection is used in Kernel and Supervisor modes, and in the User mode when the RE bit is 0. Setting the RE bit to 1 inverts the User mode endianness.

Status Register Format

Figure 5-5 shows the format of the Status register. Table 5-3 describes the Status register fields. Figure 5-6 and Table 5-4 provide additional information on the Diagnostic Status (DS) field. All bits in the DS field except TS are readable and writable.

Figure 5-5 Status Register

Table 5-3 Status Register Fields

Table 5-3 (cont.) Status Register Fields

Figure 5-6 Status Register DS Field

Table 5-4 Status Register Diagnostic Status Bits

Status Register Modes and Access States

Fields of the Status register set the modes and access states described in the sections that follow.

Interrupt Enable: Interrupts are enabled when all of the following conditions are true:

IE = 1
EXL = 0
ERL = 0

If these conditions are met, the settings of the IM bits enable the interrupt.

Operating Modes: The following CPU Status register bit settings are required for User, Kernel, and Supervisor modes (see Chapter 4 for more information about operating modes).

The processor is in User mode when KSU = 102, EXL = 0, and ERL = 0.

The processor is in Supervisor mode when KSU = 012, EXL = 0, and ERL = 0.

The processor is in Kernel mode when KSU = 002, or EXL = 1, or ERL = 1.

32- and 64-bit Modes: The following CPU Status register bit settings select 32- or 64-bit operation for User, Kernel, and Supervisor operating modes. Enabling 64-bit operation permits the execution of 64-bit opcodes and translation of 64-bit addresses. 64-bit operation for User, Kernel and Supervisor modes can be set independently.

64-bit addressing for Kernel mode is enabled when KX = 1. 64-bit operations are always valid in Kernel mode.
64-bit addressing and operations are enabled for Supervisor mode when SX = 1.
64-bit addressing and operations are enabled for User mode when UX = 1.

Kernel Address Space Accesses: Access to the kernel address space is allowed when the processor is in Kernel mode.

Supervisor Address Space Accesses: Access to the supervisor address space is allowed when the processor is in Kernel or Supervisor mode, as described above in the section above titled, Operating Modes.

User Address Space Accesses: Access to the user address space is allowed in any of the three operating modes.

Status Register Reset

The contents of the Status register are undefined at reset, except for the following bits in the Diagnostic Status field:

TS = 0
ERL and BEV = 1

The SR bit distinguishes between the Reset exception and the Soft Reset exception (caused either by Reset* or Nonmaskable Interrupt [NMI]).

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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