4.3 System Control Coprocessor
TLB Misses
If there is no TLB entry that matches the virtual address, a TLB miss exception occurs.*1 If the access control bits (D and V) indicate that the access is not valid, a TLB modification or TLB invalid exception occurs. If the C bits equal 0102, the physical address that is retrieved accesses main memory, bypassing the cache.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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