4.3 System Control Coprocessor
CP0 Registers
The following sections describe the CP0 registers, shown in Figure 4-7, that are assigned specifically as a software interface with memory management (each register is followed by its register number in parentheses).
- Index register (CP0 register number 0)
- Random register (1)
- EntryLo0 (2) and EntryLo1 (3) registers
- PageMask register (5)
- Wired register (6)
- EntryHi register (10)
- PRId register (15)
- Config register (16)
- LLAddr register (17)
- TagLo (28) and TagHi (29) registers
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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