4.3 System Control Coprocessor

Format of a TLB Entry

Figure 4-8 shows the TLB entry formats for both 32- and 64-bit modes. Each field of an entry has a corresponding field in the EntryHi, EntryLo0, EntryLo1, or PageMask registers, as shown in Figures 4-9 and 4-10; for example the Mask field of the TLB entry is also held in the PageMask register.



Figure 4-8 Format of a TLB Entry

The format of the EntryHi, EntryLo0, EntryLo1, and PageMask registers are nearly the same as the TLB entry. The one exception is the Global field
(G bit), which is used in the TLB, but is reserved in the EntryHi register. Figures 4-9 and 4-10 describe the TLB entry fields shown in Figure 4-8.



Figure 4-9 Fields of the PageMask and EntryHi Registers



Figure 4-10 Fields of the EntryLo0 and EntryLo1 Registers

The TLB page coherency attribute (C) bits specify whether references to the page should be cached; if cached, the algorithm selects between several coherency attributes. Table 4-6 shows the coherency attributes selected by the C bits.

Table 4-6 TLB Page Coherency (C) Bit Values

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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