4. Memory Management
4.3 System Control Coprocessor
The System Control Coprocessor (CP0) is implemented as an integral part of the CPU, and supports memory management, address translation, exception handling, and other privileged operations. CP0 contains the registers shown in Figure 4-7 plus a 48entry TLB. The sections that follow describe how the processor uses the memory management-related registers*1.
Each CP0 register has a unique number that identifies it; this number is referred to as the register number. For instance, the Page Mask register is register number 5.
Figure 4-7 CP0 Registers and the TLB
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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