Overview of the Contents

Chapter 2 is an overview of the CPU instruction set.

Chapter 3 describes the operation of the R4000 instruction execution pipeline, including the basic operation of the pipeline and interruptions that are caused by interlocks and exceptions.

Chapter 4 describes the memory management system including address mapping and address spaces, virtual memory, the translation lookaside buffer (TLB), and the System Control Processor (CP0).

Chapter 5 describes the exception processing resources of R4000 processor. It includes an overview of the CPU exception handling process and describes the format and use of each CPU exception handling register.

Chapter 6 describes the Floating-Point Unit (FPU), a coprocessor for the CPU that extends the CPU instruction set to perform floating-point arithmetic operations. This chapter lists the FPU registers and instructions.

Chapter 7 describes the FPU exception processing.

Chapter 8 describes the signals that pass between the R4000 processor and other components in a system. The signals discussed include the System interface, the Clock/Control interface, the Secondary Cache interface, the Interrupt interface, the Initialization interface, and the JTAG interface.

Chapter 9 describes in more detail the Initialization interface, which includes the boot modes for the processor, as well as system resets.

Chapter 10 describes the clocks used in the R4000 processor, as well as the processor status reporting mechanism.

Chapter 11 discusses cache memory, including the operation of the primary and secondary caches, and cache coherency in a multiprocessor system.

Chapter 12 describes the System interface, which allows the processor access to external resources such as memory and input/output (I/O). It also allows an external agent access to the internal resources of the processor, such as the secondary cache.

Chapter 13 describes the Secondary Cache interface, including read and write cycle timing. This chapter also discusses the interface buses and signals.

Chapter 14 describes the Joint Test Action Group (JTAG) interface. The JTAG boundary scan mechanism tests the interconnections between the R4000 processor, the printed circuit board to which it is mounted, and other components on the board.

Chapter 15 describes the single nonmaskable processor interrupt, along with the six hardware and two software processor interrupts.

Chapter 16 describes the error checking and correcting (ECC) mechanisms of the R4000 processor.

Appendix A describes the R4000 CPU instructions, in both 32- and 64-bit modes. The instruction list is given in alphabetical order.

Appendix B describes the R4000 FPU instructions, listed alphabetically.

Appendix C describes sub-block ordering, a nonsequential method of retrieving data.

Appendix D describes the output buffer and the Di/Dt control mechanism.

Appendix E describes the passive components that make up the phase-locked loop (PLL).

Appendix F describes Coprocessor 0 hazards.

Appendix G describes the R4000 pinout.

A range of bits uses a colon as a separator; for instance, (15:0) represents the 16-bit range that runs from bit 0, inclusive, through bit 15. (In some places an ellipsis may used in place of the colon for visibility: (15...0).)

Chapter Contents