4. Memory Management
4.1 Translation Lookaside Buffer (TLB)
Mapped virtual addresses are translated into physical addresses using an on-chip TLB.*1 The TLB is a fully associative memory that holds 48 entries, which provide mapping to 48 odd/even page pairs (96 pages). When address mapping is indicated, each TLB entry is checked simultaneously for a match with the virtual address that is extended with an ASID stored in the EntryHi register.
The address mapped to a page ranges in size from 4 Kbytes to 16 Mbytes, in multiples of 4--that is, 4K, 16K, 64K, 256K, 1M, 4M, 16M.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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