R4400 Microprocessor User's Manual

4. Memory Management

The MIPS R4000 processor provides a full-featured memory management unit (MMU) which uses an on-chip translation lookaside buffer (TLB) to translate virtual addresses into physical addresses.

This chapter describes the processor virtual and physical address spaces, the virtual-to-physical address translation, the operation of the TLB in making these translations, and those System Control Coprocessor (CP0) registers that provide the software interface to the TLB.

Chapter Contents

4.1 - Translation Lookaside Buffer (TLB)
4.2 - Address Spaces
4.3 - System Control Coprocessor

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