D Output Buffer Di/Dt Control Mechanism

D.1 Mode Bits

Four bits are used to control the pull-up and pull-down delays. These bits are initially set to the values in the mode bits InitN(3:0) for pull-up and InitP(3:0) for pull-down. If the Di/Dt control mechanism is enabled, it is recommended to load the mode bits InitP(3:0) and InitN(3:0) to the values which provide the slowest slew rate.

Under normal conditions, the Di/Dt control mechanism is enabled to compensate the output buffer delay for any changes in the temperature or power supply voltage. The EnblDPLL mode bit is set for this mode of operation.

For situations where the jitter associated with the operation of the Di/Dt control mechanism cannot be tolerated and where the variation in temperature and supply voltage after ColdReset* is expected to be small, the Di/Dt control mechanism can be instructed to lock during ColdReset* and thereafter retain its control values. The EnblDPLLR mode bit is set and EnblDPLL is cleared for this mode of operation.

In addition, if both the EnblDPLL and EnblDPLLR mode bits are cleared, the speed of the output buffers are set by the InitP(3:0) and InitN(3:0) mode bits.

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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