Global Table of Contents

Second Edition
http://www.mips.com
Acknowledgments for the First Edition
Acknowledgments for the Second Edition
Preface to the First Edition
Overview of the Contents
A Note on Style
Preface to the Second Edition
Changes From the First Edition
Getting MIPS Documents On-Line
1. - Introduction
1.1 - Benefits of RISC Design
Shorter Design Cycle
Effective Utilization of Chip Area
User (Programmer) Benefits
Advanced Semiconductor Technologies
Optimizing Compilers
MIPS RISCompiler Language Suite
1.2 - Compatibility
1.3 - Processor General Features
1.4 - R4000 Processor Configurations
1.5 - R4400 Processor Enhancements
1.6 - R4000 Processor
64-bit Architecture
Superpipeline Architecture
System Interface
CPU Register Overview
CPU Instruction Set Overview
Data Formats and Addressing
Coprocessors (CP0-CP2)
System Control Coprocessor, CP0
Floating-Point Unit (FPU), CP1
Memory Management System (MMU)
The Translation Lookaside Buffer (TLB)
Instruction TLB
Joint TLB
Operating Modes
Cache Memory Hierarchy
Primary Caches
Secondary Cache Interface
2. - CPU Instruction Set Summary
2.1 - CPU Instruction Formats
Load and Store Instructions
Scheduling a Load Delay Slot
Defining Access Types
Computational Instructions
64-bit Operations
Cycle Timing for Multiply and Divide Instructions
Jump and Branch Instructions
Overview of Jump Instructions
Overview of Branch Instructions
Special Instructions
Exception Instructions
Coprocessor Instructions
3. - The CPU Pipeline
3.1 - CPU Pipeline Operation
CPU Pipeline Stages
IF - Instruction Fetch, First Half
IS - Instruction Fetch, Second Half
RF - Register Fetch
EX - Execution
DF - Data Fetch, First Half
DS - Data Fetch, Second Half
TC - Tag Check
WB - Write Back
3.2 - Branch Delay
3.3 - Load Delay
3.4 - Interlock and Exception Handling
Exception Conditions
Stall Conditions
Slip Conditions
External Stalls
Interlock and Exception Timing
Backing Up the Pipeline
Aborting an Instruction Subsequent to an Interlock
Pipelining the Exception Handling
Special Cases
Performance Considerations
Address Acceleration
Address Prediction
Correctness Considerations
3.5 - R4400 Processor Uncached Store Buffer
4. - Memory Management
4.1 - Translation Lookaside Buffer (TLB)
Hits and Misses
Multiple Matches
4.2 - Address Spaces
Virtual Address Space
Physical Address Space
Virtual-to-Physical Address Translation
32-bit Mode Address Translation
64-bit Mode Address Translation
Operating Modes
User Mode Operations
32-bit User Mode (useg)
64-bit User Mode (xuseg)
Supervisor Mode Operations
32-bit Supervisor Mode, User Space (suseg)
32-bit Supervisor Mode, Supervisor Space (sseg)
64-bit Supervisor Mode, User Space (xsuseg)
64-bit Supervisor Mode, Current Supervisor Space (xsseg)
64-bit Supervisor Mode, Separate Supervisor Space (csseg)
Kernel Mode Operations
32-bit Kernel Mode, User Space (kuseg)
32-bit Kernel Mode, Kernel Space 0 (kseg0)
32-bit Kernel Mode, Kernel Space 1 (kseg1)
32-bit Kernel Mode, Supervisor Space (ksseg)
32-bit Kernel Mode, Kernel Space 3 (kseg3)
64-bit Kernel Mode, User Space (xkuseg)
64-bit Kernel Mode, Current Supervisor Space (xksseg)
64-bit Kernel Mode, Physical Spaces (xkphys)
64-bit Kernel Mode, Kernel Space (xkseg)
64-bit Kernel Mode, Compatibility Spaces (ckseg1:0, cksseg, ckseg3)
4.3 - System Control Coprocessor
Format of a TLB Entry
CP0 Registers
Index Register (0)
Random Register (1)
EntryLo0 (2), and EntryLo1 (3) Registers
PageMask Register (5)
Wired Register (6)
EntryHi Register (CP0 Register 10)
Processor Revision Identifier (PRId) Register (15)
Config Register (16)
Load Linked Address (LLAddr) Register (17)
Cache Tag Registers [TagLo (28) and TagHi (29)]
Virtual-to-Physical Address Translation Process
TLB Misses
TLB Instructions
5. - CPU Exception Processing
5.1 - How Exception Processing Works
5.2 - Exception Processing Registers
Context Register (4)
Bad Virtual Address Register (BadVAddr) (8)
Count Register (9)
Compare Register (11)
Status Register (12)
Status Register Format
Status Register Modes and Access States
Status Register Reset
Cause Register (13)
Exception Program Counter (EPC) Register (14)
WatchLo (18) and WatchHi (19) Registers
XContext Register (20)
Error Checking and Correcting (ECC) Register (26)
Cache Error (CacheErr) Register (27)
Error Exception Program Counter (Error EPC) Register (30)
5.3 - Processor Exceptions
Exception Types
Reset Exception Process
Cache Error Exception Process
Soft Reset and NMI Exception Process
General Exception Process
Exception Vector Locations
Priority of Exceptions
Reset Exception
Soft Reset Exception
Address Error Exception
TLB Exceptions
TLB Refill Exception
Cause
Processing
Servicing
TLB Invalid Exception
Cause
Processing
Servicing
TLB Modified Exception
Cause
Processing
Servicing
Cache Error Exception
Virtual Coherency Exception
Bus Error Exception
Integer Overflow Exception
Trap Exception
System Call Exception
Breakpoint Exception
Reserved Instruction Exception
Coprocessor Unusable Exception
Floating-Point Exception
Watch Exception
Interrupt Exception
5.4 - Exception Handling and Servicing Flowcharts
6. - Floating-Point Unit
6.1 - Overview
6.2 - FPU Features
6.3 - FPU Programming Model
Floating-Point General Registers (FGRs)
Floating-Point Registers
Floating-Point Control Registers
Implementation and Revision Register, (FCR0)
Control/Status Register (FCR31)
Accessing the Control/Status Register
IEEE Standard 754
Control/Status Register FS Bit
Control/Status Register Condition Bit
Control/Status Register Cause, Flag, and Enable Fields
Cause Bits
Enable Bits
Flag Bits
Control/Status Register Rounding Mode Control Bits
6.4 - Floating-Point Formats
6.5 - Binary Fixed-Point Format
6.6 - Floating-Point Instruction Set Overview
Floating-Point Load, Store, and Move Instructions
Transfers Between FPU and Memory
Transfers Between FPU and CPU
Load Delay and Hardware Interlocks
Data Alignment
Endianness
Floating-Point Conversion Instructions
Floating-Point Computational Instructions
Branch on FPU Condition Instructions
Floating-Point Compare Operations
6.7 - FPU Instruction Pipeline Overview
Instruction Execution
Instruction Execution Cycle Time
Scheduling FPU Instructions
FPU Pipeline Overlapping
Instruction Scheduling Constraints
FPU Divider Constraints
FPU Multiplier Constraints
FPU Adder Constraints
Instruction Latency, Repeat Rate, and Pipeline Stage Sequences
Resource Scheduling Rules
7. - Floating-Point Exceptions
7.1 - Exception Types
7.2 - Exception Trap Processing
7.3 - Flags
7.4 - FPU Exceptions
Inexact Exception (I)
Invalid Operation Exception (V)
Division-by-Zero Exception (Z)
Overflow Exception (O)
Underflow Exception (U)
Unimplemented Instruction Exception (E)
7.5 - Saving and Restoring State
7.6 - Trap Handlers for IEEE Standard 754 Exceptions
8. - R4000 Processor Signal Descriptions
8.1 - System Interface Signals
8.2 - Clock/Control Interface Signals
8.3 - Secondary Cache Interface Signals
8.4 - Interrupt Interface Signals
8.5 - JTAG Interface Signals
8.6 - Initialization Interface Signals
8.7 - Signal Summary
9. - Initialization Interface
9.1 - Functional Overview
9.2 - Reset Signal Description
Power-on Reset
Cold Reset
Warm Reset
9.3 - Initialization Sequence
9.4 - Boot-Mode Settings
10. - Clock Interface
10.1 - Signal Terminology
10.2 - Basic System Clocks
MasterClock
MasterOut
SyncIn/SyncOut
PClock
SClock
TClock
RClock
PClock-to-SClock Division
10.3 - System Timing Parameters
Alignment to SClock
Alignment to MasterClock
Phase-Locked Loop (PLL)
10.4 - Connecting Clocks to a Phase-Locked System
10.5 - Connecting Clocks to a System without Phase Locking
Connecting to a Gate-Array Device
Connecting to a CMOS Logic System
10.6 - Processor Status Outputs
11. - Cache Organization, Operation, and Coherency
11.1 - Memory Organization
11.2 - Overview of Cache Operations
11.3 - R4000 Cache Description
Secondary Cache Size
Variable-Length Cache Lines
Cache Organization and Accessibility
Organization of the Primary Instruction Cache (I-Cache)
Organization of the Primary Data Cache (D-Cache)
Accessing the Primary Caches
Organization of the Secondary Cache
Accessing the Secondary Cache
11.4 - Cache States
Primary Cache States
Secondary Cache States
Mapping States Between Caches
11.5 - Cache Line Ownership
11.6 - Cache Write Policy
11.7 - Cache State Transition Diagrams
11.8 - Cache Coherency Overview
Cache Coherency Attributes
Uncached
Noncoherent
Sharable
Update
Exclusive
Cache Operation Modes
Secondary-Cache Mode
No-Secondary-Cache Mode
Strong Ordering
An Example of Strong Ordering
Testing for Strong Ordering
Restarting the Processor
Restart after a Coherent Read Request
Restart after a Coherent Write Request
Restart after an Invalidate or Update Request
11.9 - Maintaining Coherency on Loads and Stores
11.10 - Manipulation of the Cache by an External Agent
Invalidate
Update
Snoop
Intervention
11.11 - Coherency Conflicts
How Coherency Conflicts Arise
Processor Coherent Read Requests
Processor Invalidate or Update Requests
External Coherency Requests
System Implications of Coherency Conflicts
System Model
Load
Store
Processor Coherent Read Request and Read Response
Ordinary Read Request
Read Exclusive Request
Processor Invalidate
Processor Write
Handling Coherency Conflicts
Coherent Read Conflicts
Coherent Write Conflicts
Invalidate Conflicts
Sample Cycle: Coherent Read Request
11.12 - R4000 Processor Synchronization Support
Test-and-Set (Spinlock)
Counter
LL and SC
Examples Using LL and SC
12. - System Interface
12.1 - Terminology
12.2 - System Interface Description
Interface Buses
Address and Data Cycles
Issue Cycles
Handshake Signals
12.3 - System Interface Protocols
Master and Slave States
Moving from Master to Slave State
External Arbitration
Uncompelled Change to Slave State
12.4 - Processor and External Requests
Rules for Processor Requests
Processor Requests
Processor Read Request
Processor Write Request
Processor Invalidate Request
Processor Update Request
Clusters
Read With Write Forthcoming Request as Part of a Cluster
Potential Update as Part of a Cluster
Write Request as Part of a Cluster
Null Write Request as Part of a Cluster
External Requests
External Read Request
External Write Request
External Invalidate Request
External Update Request
External Snoop Request
External Intervention Request
Read Response
12.5 - Handling Requests
Load Miss
Secondary-Cache Mode
No-Secondary-Cache Mode
Store Miss
Secondary-Cache Mode
Noncoherent Page Attribute
Sharable or Exclusive Page Attribute
Update Page Attribute
No-Secondary-Cache Mode
Store Hit
Secondary-Cache Mode
No-Secondary-Cache Mode
Uncached Loads or Stores
CACHE Operations
Load Linked Store Conditional Operation
12.6 - Processor and External Request Protocols
Processor Request Protocols
Processor Read Request Protocol
Processor Write Request Protocol
Processor Invalidate and Update Request Protocol
Processor Null Write Request Protocol
Processor Cluster Request Protocol
Processor Request and Cluster Flow Control
External Request Protocols
External Arbitration Protocol
External Read Request Protocol
External Null Request Protocol
External Write Request Protocol
External Invalidate and Update Request Protocols
External Intervention Request Protocol
External Snoop Request Protocol
Read Response Protocol
12.7 - Data Rate Control
Data Transfer Patterns
Secondary Cache Transfers
Secondary Cache Write Cycle Time
Independent Transmissions on the SysAD Bus
System Interface Endianness
12.8 - System Interface Cycle Time
Cluster Request Spacing
Release Latency
External Request Response Latency
12.9 - System Interface Commands and Data Identifiers
Command and Data Identifier Syntax
System Interface Command Syntax
Read Requests
Write Requests
Null Requests
Invalidate Requests
Update Requests
Intervention and Snoop Requests
System Interface Data Identifier Syntax
Coherent Data
Noncoherent Data
Data Identifier Bit Definitions
12.10 - System Interface Addresses
Addressing Conventions
Sequential and Subblock Ordering
12.11 - Processor Internal Address Map
13. - Secondary Cache Interface
13.1 - Data Transfer Rates
13.2 - Duplicating Signals
13.3 - Accessing a Split Secondary Cache
13.4 - SCDChk Bus
13.5 - SCTAG Bus
13.6 - Operation of the Secondary Cache Interface
Read Cycles
4-Word Read Cycle
8-Word Read Cycle
Notes on a Secondary Cache Read Cycle
Write Cycles
4-Word Write Cycle
8-Word Write Cycle
Notes on a Secondary Cache Write Cycle
14. - JTAG Interface
14.1 - What Boundary Scanning Is
14.2 - Signal Summary
14.3 - JTAG Controller and Registers
Instruction Register
Bypass Register
Boundary-Scan Register
Test Access Port (TAP)
TAP Controller
Controller Reset
Controller States
14.4 - Implementation-Specific Details
15. - R4000 Processor Interrupts
15.1 - Hardware Interrupts
15.2 - Nonmaskable Interrupt (NMI)
15.3 - Asserting Interrupts
16. - Error Checking and Correcting
16.1 - Error Checking in the Processor
Types of Error Checking
Parity Error Detection
SECDED ECC Code
Secondary Cache Data Bus SECDED Code
Secondary Cache Tag Bus SECDED Code
Error Checking Operation
System Interface
Secondary Cache Data Bus
System Interface and Secondary Cache Data Bus
Secondary Cache Tag Bus
System Interface Command Bus
SECDED ECC Matrices for Data and Tag Buses
ECC Check Bits
Data ECC Generation
Detecting Data Transmission Errors
Single Data Bit ECC Error
Single Check Bit ECC Error
Double Data Bit ECC Errors
Three Data Bit ECC Errors
Four Data Bit ECC Errors
Tag ECC Generation
Summary of ECC Operations
16.2 - R4400 Master/Checker Mode
Connecting a System in Lock Step
Master-Listener Configuration
Cross-Coupled Checking Configuration
Fault Detection
Reset Operation
Fault History
A - CPU Instruction Set Details
A.1 - Instruction Classes
A.2 - Instruction Formats
A.3 - Instruction Notation Conventions
Instruction Notation Examples
A.4 - Load and Store Instructions
A.5 - Jump and Branch Instructions
A.6 - Coprocessor Instructions
A.7 - System Control Coprocessor (CP0) Instructions
Format:
CPU Instruction Opcode Bit Encoding
B - FPU Instruction Set Details
B.1 - Instruction Formats
Floating-Point Loads, Stores, and Moves
Floating-Point Operations
B.2 - Instruction Notation Conventions
Instruction Notation Examples
B.3 - Load and Store Instructions
B.4 - Computational Instructions
FPU Instruction Opcode Bit Encoding
C - Subblock Ordering
C.1 - Sequential Ordering
C.2 - Subblock Ordering
D - Output Buffer Di/Dt Control Mechanism
D.1 - Mode Bits
D.2 - Delay Times
E - PLL Passive Components
F - Coprocessor 0 Hazards
G - R4000 Pinouts
G.1 - Pinout of R4000PC
G.2 - Pinout of R4000MC/SC Package Pinout
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