B FPU Instruction Set Details

SWC1 ft, offset(base)

Description:

The 16-bit offset is sign-extended and added to the contents of general register base to form an unsigned effective address. The contents of register ft from the floating-point coprocessor are stored at the memory location specified by the effective address.

The FR bit of the Status register specifies whether all 64-bit floating-point registers are addressable.

If FR equals zero, SWC1 stores either the high or low half of the 16 even floating-point registers.

If FR equals one, SWC1 stores the low 32-bits of both even and odd floating-point registers.

If either of the two least-significant bits of the effective address are non-zero, an address error exception occurs.

Operation:

Exceptions:

Coprocessor unusable
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception

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