B FPU Instruction Set Details

SDC1 ft, offset(base)

Description:

The 16-bit offset is sign-extended and added to the contents of general register base to form an unsigned effective address.

In 32-bit mode, the contents of registers ft and ft+1 from the floating-point coprocessor are stored at the memory location specified by the effective address. This instruction is not valid, and is undefined, when the least significant bit of ft is non-zero.

In 64-bit mode, the 64-bit register ft is stored to the contents of the doubleword at the memory location specified by the effective address. The FR bit of the Status register (SR26) specifies whether all 32 registers of the R4000 are addressable. When FR equals zero, this instruction is not defined if the least significant bit of ft is non-zero. If FR equals one, ft may specify either odd or even registers.

If any of the three least-significant bits of the effective address are non-zero, an address error exception takes place.

Operation:

Exceptions:

Coprocessor unusable
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception

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