B FPU Instruction Set Details

MTC1 rt, fs

Description:

The contents of register rt are loaded into the FPU general register at location fs.

The contents of floating-point register fs is undefined for the instruction immediately following MTC1.

The FR bit of the Status register specifies whether all 32 registers of the R4000 are addressable. If FR equals zero, MTC1 loads either the high or low half of the 16 even Floating-Point registers. If FR equals one, MTC1 loads the low 32-bits of both even and odd Floating-Point registers.

Operation:

Exceptions:

Coprocessor unusable exception

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