B FPU Instruction Set Details

MFC1 rt, fs

Description:

The contents of register fs from the floating-point coprocessor are stored into processor register rt.

The contents of register rt are undefined for the instruction immediately following MFC1.

The FR bit of the Status register specifies whether all 32 registers of the R4000 are addressable. If FR equals zero, MFC1 stores either the high or low half of the 16 even Floating-Point registers. If FR equals one, MFC1 stores the low 32-bits of both even and odd Floating-Point registers.

Operation:

Exceptions:

Coprocessor unusable exception

Generated with CERN WebMaker