B FPU Instruction Set Details

LWC1 ft, offset(base)

Description:

The 16-bit offset is sign-extended and added to the contents of general register base to form an unsigned effective address. The contents of the word at the memory location specified by the effective address is loaded into register ft of the floating-point coprocessor.

The FR bit of the Status register specifies whether all 64-bit Floating-Point registers are addressable. If FR equals zero, LWC1 loads either the high or low half of the 16 even Floating-Point registers. If FR equals one, LWC1 loads the low 32-bits of both even and odd Floating-Point registers.

If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs.

Operation:

Exceptions:

Coprocessor unusable
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception

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