B FPU Instruction Set Details

LDC1 ft, offset(base)

Description:

The 16-bit offset is sign-extended and added to the contents of general register base to form an unsigned effective address.

In 32-bit mode, the contents of the doubleword at the memory location specified by the effective address is loaded into registers ft and ft+1 of the floating-point coprocessor. This instruction is not valid, and is undefined, when the least significant bit of ft is non-zero.

In 64-bit mode, the contents of the doubleword at the memory location specified by the effective address are loaded into the 64-bit register ft of the floating point coprocessor.

The FR bit of the Status register (SR26) specifies whether all 32 registers of the R4000 are addressable. If FR equals zero, this instruction is not defined when the least significant bit of ft is non-zero. If FR equals one, ft may specify either odd or even registers.

If any of the three least-significant bits of the effective address are non-zero, an address error exception takes place.

Operation:

Exceptions:

Coprocessor unusable
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception

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