B FPU Instruction Set Details

DMFC1 rt, fs

Description:

The contents of register fs from the floating-point coprocessor is stored into processor register rt.

The contents of general register rt are undefined for the instruction immediately following DMFC1.

The FR bit in the Status register specifies whether all 32 registers of the R4000 are addressable. When FR equals zero, this instruction is not defined when the least significant bit of fs is non-zero. When FR is set, fs may specify either odd or even registers.

Operation:

Exceptions:

Coprocessor unusable exception

Coprocessor Exceptions:

Unimplemented operation exception

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