B FPU Instruction Set Details

DIV.fmt fd, fs, ft

Description:

The contents of the floating-point registers specified by fs and ft are interpreted in the specified format and the value in the fs field is divided by the value in the ft field. The result is rounded as if calculated to infinite precision and then rounded to the specified format, according to the current rounding mode. The result is placed in the floating-point register specified by fd.

This instruction is valid for only single or double precision floating-point formats.

The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero, since the register numbers specify an even-odd pair of adjacent coprocessor general registers. When the FR bit in the Status register equals one, both even and odd register numbers are valid.

Operation:

Exceptions:

Coprocessor unusable exception
Floating-Point exception

Coprocessor Exceptions:

Unimplemented operation exception Invalid operation exception
Division-by-zero exception Inexact exception
Overflow exception Underflow exception

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