3.4 Interlock and Exception Handling

Pipelining the Exception Handling

In particular, a half clock period is provided for buffering and distributing the run control signal; during this time the logic evaluation to produce run for the next cycle begins. Figure 3-9 shows this process for a sequence of loads.

Figure 3-9 Pipelining of Interlock and Exception Handling

The decision whether or not to advance the pipeline is derived from these three rules:

• All possible fault-causing events, such as cache misses, translation exceptions, load interlocks, etc., must be individually evaluated.
• The fault to be serviced is selected, based on a predefined priority as determined by the pipeline stage of the asserted faults.
• Pipeline advance control signals are buffered and distributed.

Figure 3-10 Pipeline Advance Decision

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