B FPU Instruction Set Details

CTC1 rt, fs

Description:

The contents of general register rt are loaded into FPU control register fs. This operation is only defined when fs equals 0 or 31.

Writing to Control Register 31, the floating-point Control/Status register, causes an interrupt or exception if any cause bit and its corresponding enable bit are both set. The register will be written before the exception occurs. The contents of floating-point control register fs are undefined for the instruction immediately following CTC1.

Operation:

Exceptions:

Coprocessor unusable exception
Floating-Point exception

Coprocessor Exceptions:

Unimplemented operation exception
Invalid operation exception
Division by zero exception
Inexact exception
Overflow exception
Underflow exception

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