B FPU Instruction Set Details



Format:

CFC1 rt, fs

Description:

The contents of the FPU control register fs are loaded into general register rt.

This operation is only defined when fs equals 0 or 31.

The contents of general register rt are undefined for the instruction immediately following CFC1.

Operation:

Exceptions:

Coprocessor unusable exception

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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