B FPU Instruction Set Details

C.cond.fmt fs, ft

Description:

The contents of the floating-point registers specified by fs and ft are interpreted in the specified format, fmt, and arithmetically compared.

A result is determined based on the comparison and the conditions specified in the cond field. If one of the values is a Not a Number (NaN), and the high-order bit of the cond field is set, an invalid operation exception is taken. After a one-instruction delay, the condition is available for testing with branch on floating-point coprocessor condition instructions. There must be at least one instruction between the compare and the branch.

Comparisons are exact and can neither overflow nor underflow. Four mutually-exclusive relations are possible results: less than, equal, greater than, and unordered. The last case arises when one or both of the operands are NaN; every NaN compares unordered with everything, including itself.

Comparisons ignore the sign of zero, so +0 = -0.

This instruction is valid only for single- and double-precision floating-point formats. The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero, since the register numbers specify an even-odd pair of adjacent coprocessor general registers. When the FR bit in the Status register equals one, both even and odd register numbers are valid.

*See "FPU Instruction Opcode Bit Encoding" at the end of Appendix B.

Operation:

Exceptions:

Coprocessor unusable
Floating-Point exception

Coprocessor Exceptions:

Unimplemented operation exception
Invalid operation exception

Generated with CERN WebMaker