-Interlock and Exception Timing

3.4 Interlock and Exception Handling

Interlock and Exception Timing

To prevent interlock and exception handling from adversely affecting the processor cycle time, the R4000 processor uses both logic and circuit pipeline techniques to reduce critical timing paths. Interlock and exception handling have the following effects on the pipeline:

In some cases, the processor pipeline must be backed up (reversed and started over again from a prior stage) to recover from interlocks.
In some cases, interlocks are serviced for instructions that will be aborted, due to an exception.

These two cases are discussed below.

Backing Up the Pipeline

An example of pipeline back-up occurs in a data cache miss, in which the late detection of the miss causes a subsequent instruction to compute an incorrect result.

When this occurs, not only must the cache miss be serviced but the EX stage of the dependent instruction must be re-executed before the pipeline can be restarted. Figure 3-7 illustrates this procedure; a minus (-) after
the pipeline stage descriptor (for instance, EX-) indicates the operation produced an incorrect result, while a plus (+) indicates the successful
re-execution of that operation.

Figure 3-7 Pipeline Overrun

Aborting an Instruction Subsequent to an Interlock

The interaction between an integer overflow and an instruction cache miss is an example of an interlock being serviced for an instruction that is subsequently aborted.

In this case, pipelining the overflow exception handling into the DF stage allows an instruction cache miss to occur on the next immediate instruction. Figure 3-8 illustrates this; aborted instructions are indicated with an asterisk (*).

Figure 3-8 Instruction Cache Miss

Even though the line brought in by the instruction cache could have been replaced by a line of the exception handler, no performance loss occurs, since the instruction cache miss would have been serviced anyway, after returning from the exception handler. Handling of the exception is done in this fashion because the frequency of an exception occurring is, by definition, relatively low.

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