B.4 -Computational Instructions

B FPU Instruction Set Details

B.4 Computational Instructions

Computational instructions include all of the arithmetic floating-point operations performed by the FPU.

Figure B-2 shows the R-Type instruction format used for computational operations.

Figure B-2 Computational Instruction Format

The function field indicates the floating-point operation to be performed.

Each floating-point instruction can be applied to a number of operand formats. The operand format for an instruction is specified by the 5bit format field; decoding for this field is shown in Table B-4.

Table B-4 Format Field Decoding

Table B-5 lists all floating-point instructions.

Table B-5 Floating-Point Instructions and Operations

In the following pages, the notation FGR refers to the 32 General Purpose registers FGR0 through FGR31 of the FPU, and FPR refers to the floating-point registers of the FPU.

When the FR bit in the Status register (SR(26)) equals zero, only the even floating-point registers are valid and the 32 General Purpose registers of the FPU are 32-bits wide.
When the FR bit in the Status register (SR(26)) equals one, both odd and even floating-point registers may be used and the 32 General Purpose registers of the FPU are 64-bits wide.

The following routines are used in the description of the floating-point operations to retrieve the value of an FPR or to change the value of an FGR:

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