B.3 -Load and Store Instructions

B FPU Instruction Set Details

B.3 Load and Store Instructions

In the R4000 implementation, the instruction immediately following a load may use the contents of the register being loaded. In such cases, the hardware interlocks, requiring additional real cycles, so scheduling load delay slots is still desirable, although not required for functional code.

The behavior of the load store instructions is dependent on the width of the FGRs.

When the FR bit in the Status register equals zero, the Floating-Point General registers (FGRs) are 32-bits wide.
When the FR bit in the Status register equals one, the Floating-Point General registers (FGRs) are 64-bits wide.

In the load and store operation descriptions, the functions listed in
Table B-3 are used to summarize the handling of virtual addresses and physical memory.

Table B-3 Load and Store Common Functions

Figure B-1 shows the I-Type instruction format used by load and store operations.

Figure B-1 Load and Store Instruction Format

All coprocessor loads and stores reference aligned data items. Thus, for word loads and stores, the access type field is always WORD, and the low-order two bits of the address must always be zero.

For doubleword loads and stores, the access type field is always DOUBLEWORD, and the low-order three bits of the address must always be zero.

Regardless of byte-numbering order (endianness), the address specifies that byte which has the smallest byte-address in the addressed field. For a big-endian machine, this is the leftmost byte; for a little-endian machine, this is the rightmost byte.

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