B.1 -Instruction Formats

B FPU Instruction Set Details

B.1 Instruction Formats

There are three basic instruction format types:

I-Type, or Immediate instructions, which include load and store operations
M-Type, or Move instructions
R-Type, or Register instructions, which include the two- and three-register floating-point operations.

The instruction description subsections that follow show how these three basic instruction formats are used by:

Load and store instructions
Move instructions
Floating-Point computational instructions
Floating-Point branch instructions

Floating-point instructions are mapped onto the MIPS coprocessor instructions, defining coprocessor unit number one (CP1) as the floating-point unit.

Each operation is valid only for certain formats. Implementations may support some of these formats and operations through emulation, but they only need to support combinations that are valid (marked V in Table B-1). Combinations marked R in Table B-1 are not currently specified by this architecture, and cause an unimplemented operation trap. They will be available for future extensions to the architecture.

Table B-1 Valid FPU Instruction Formats

The coprocessor branch on condition true/false instructions can be used to logically negate any predicate. Thus, the 32 possible conditions require only 16 distinct comparisons, as shown in Table B-2 below.

Table B-2 Logical Negation of Predicates by Condition True/False

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