CPU Instruction Opcode Bit Encoding
The remainder of this Appendix presents the opcode bit encoding for the CPU instruction set (ISA and extensions), as implemented by the R4000. Figure A-2 lists the R4000 Opcode Bit Encoding.
Figure A-2 R4000 Opcode Bit Encoding
Figure A-2 (cont.) R4000 Opcode Bit Encoding
Key:
- * Operation codes marked with an asterisk cause reserved instruction exceptions in all current implementations and are reserved for future versions of the architecture.
- g (gamma) Operation codes marked with a gamma cause a reserved instruction exception. They are reserved for future versions of the architecture.
- d (delta) Operation codes marked with a delta are valid only for R4000 processors with CP0 enabled, and cause a reserved instruction exception on other processors.
- f (phi) Operation codes marked with a phi are invalid but do not cause reserved instruction exceptions in R4000 implementations.
- x (xsi) Operation codes marked with a xi cause a reserved instruction exception on R4000 processors.
- c (chi) Operation codes marked with a chi are valid only on R4000.
- e (epsilon) Operation codes marked with epsilon are valid when the processor is operating either in the Kernel mode or in the 64-bit non-Kernel (User or Supervisor) mode. These instructions cause a reserved instruction exception if 64-bit operation is not enabled in User or Supervisor mode.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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