A CPU Instruction Set Details



Format:

TLBWR

Description:

The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers.

The TLB entry pointed at by the contents of the TLB Random register is loaded with the contents of the EntryHi and EntryLo registers.

Operation:

Exceptions:

Coprocessor unusable exception

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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