A CPU Instruction Set Details

TLBWI

Description:

The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers.

The TLB entry pointed at by the contents of the TLB Index register is loaded with the contents of the EntryHi and EntryLo registers.

The operation is invalid (and the results are unspecified) if the contents of the TLB Index register are greater than the number of TLB entries in the processor.

Operation:

Exceptions:

Coprocessor unusable exception

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