A CPU Instruction Set Details

TLBR

Description:

The G bit (which controls ASID matching) read from the TLB is written into both of the EntryLo0 and EntryLo1 registers.

The EntryHi and EntryLo registers are loaded with the contents of the TLB entry pointed at by the contents of the TLB Index register. The operation is invalid (and the results are unspecified) if the contents of the TLB Index register are greater than the number of TLB entries in the processor.

Operation:

Exceptions:

Coprocessor unusable exception

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