A CPU Instruction Set Details

SUBU rd, rs, rt

Description:

The contents of general register rt are subtracted from the contents of general register rs to form a result.

The result is placed into general register rd.

In 64-bit mode, the operands must be valid sign-extended, 32-bit values.

The only difference between this instruction and the SUB instruction is that SUBU never traps on overflow. No integer overflow exception occurs under any circumstances.

Operation:

Exceptions:

None

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