A CPU Instruction Set Details



Format:

SRLV rd, rt, rs

Description:

The contents of general register rt are shifted right by the number of bits specified by the low-order five bits of general register rs, inserting zeros into the high-order bits.

The result is placed in register rd.

In 64-bit mode, the operand must be a valid sign-extended, 32-bit value.

Operation:

Exceptions:

None

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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