3. The CPU Pipeline

3.4 Interlock and Exception Handling

As shown in Figure 3-5, all interlock and exception conditions are collectively referred to as faults.

Figure 3-5 Interlocks, Exceptions, and Faults

There are two types of interlocks:

• stalls, which are resolved by halting the pipeline
• slips, which require one part of the pipeline to advance while another part of the pipeline is held static

Because each exception or interlock condition corresponds to a particular pipeline stage, a condition can be traced back to the particular instruction in the exception/interlock stage, as shown in Figure 3-6. For instance, an Illegal Instruction (II) exception is raised in the execution (EX) stage.

Tables 3-1 and 3-2 describe the pipeline interlocks and exceptions listed in Figure 3-6.

Figure 3-6 Correspondence of Pipeline Stage to Interlock Condition

Table 3-1 Pipeline Exceptions

Table 3-2 Pipeline Interlocks

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