A CPU Instruction Set Details



Format:

MTC0 rt, rd

Description:

The contents of general register rt are loaded into coprocessor register rd of CP0.

Because the state of the virtual address translation system may be altered by this instruction, the operation of load instructions, store instructions, and TLB operations immediately prior to and after this instruction are undefined.

Operation:

Exceptions:

Coprocessor unusable exception

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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