A CPU Instruction Set Details



Format:

MFCz rt, rd

Description:

The contents of coprocessor register rd of coprocessor z are loaded into general register rt.

Operation:

Exceptions:

Coprocessor unusable exception

*See the table "Opcode Bit Encoding" on next page, or "CPU Instruction Opcode Bit Encoding" at the end of Appendix A.



Opcode Bit Encoding:

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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