A CPU Instruction Set Details

LWCz rt, offset(base)

Description:

The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The processor reads a word from the addressed memory location, and makes the data available to coprocessor unit z.

The manner in which each coprocessor uses the data is defined by the individual coprocessor specifications.

If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs.

This instruction is not valid for use with CP0.

*See the table "Opcode Bit Encoding" on next page, or "CPU Instruction Opcode Bit Encoding" at the end of Appendix A.

Operation:

Exceptions:

TLB refill exception TLB invalid exception
Bus error exception Address error exception
Coprocessor unusable exception

Opcode Bit Encoding:

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