A CPU Instruction Set Details

LW rt, offset(base)

Description:

The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the word at the memory location specified by the effective address are loaded into general register rt. In 64-bit mode, the loaded word is sign-extended. If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs.

Operation:

Exceptions:

TLB refill exception TLB invalid exception
Bus error exception Address error exception

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