A CPU Instruction Set Details



Format:

LHU rt, offset(base)

Description:

The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the halfword at the memory location specified by the effective address are zero-extended and loaded into general register rt.

If the least-significant bit of the effective address is non-zero, an address error exception occurs.

Operation:

Exceptions:

TLB refill exception TLB invalid exception
Bus Error exception Address error exception

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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