3.1 -CPU Pipeline Operation

3. The CPU Pipeline

3.1 CPU Pipeline Operation

The CPU has an eight-stage instruction pipeline; each stage takes one PCycle (one cycle of PClock, which runs at twice the frequency of MasterClock). Thus, the execution of each instruction takes at least eight PCycles (four MasterClock cycles). An instruction can take longer--for example, if the required data is not in the cache, the data must be retrieved from main memory.

Once the pipeline has been filled, eight instructions are executed simultaneously. Figure 3-1 shows the eight stages of the instruction pipeline; the next section describes the pipeline stages.

Figure 3-1 Instruction Pipeline Stages

CPU Pipeline Stages

This section describes each of the eight pipeline stages:

IF - Instruction Fetch, First Half
IS - Instruction Fetch, Second Half
RF - Register Fetch
EX - Execution
DF - Data Fetch, First Half
DS - Data Fetch, Second Half
TC - Tag Check
WB - Write Back

IF - Instruction Fetch, First Half

During the IF stage, the following occurs:

Branch logic selects an instruction address and the instruction cache fetch begins.

The instruction translation lookaside buffer (ITLB) begins the virtual-to-physical address translation.

The arithmetic logic unit (ALU) performs the arithmetic or logical operation for register-to-register instructions.
The ALU calculates the data virtual address for load and store instructions.
The ALU determines whether the branch condition is true and calculates the virtual branch target address for branch instructions.

DF - Data Fetch, First Half

During the DF stage, one of the following occurs:

The data cache fetch and the data virtual-to-physical translation begins for load and store instructions.

The branch instruction address translation and translation lookaside buffer (TLB)*1 update begins for branch instructions.

No operations are performed during the DF, DS, and TC stages for register-to-register instructions.

DS - Data Fetch, Second Half

During the DS stage, one of the following occurs:

The data cache fetch and data virtual-to-physical translation are completed for load and store instructions. The Shifter aligns data to its word or doubleword boundary.
The branch instruction address translation and TLB update are completed for branch instructions.

TC - Tag Check

For load and store instructions, the cache performs the tag check during the TC stage. The physical address from the TLB is checked against the cache tag to determine if there is a hit or a miss.

WB - Write Back

For register-to-register instructions, the instruction result is written back to the register file during the WB stage. Branch instructions perform no operation during this stage.

Figure 3-2 shows the activities occurring during each ALU pipeline stage, for load, store, and branch instructions.

Figure 3-2 CPU Pipeline Activities

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