A CPU Instruction Set Details

JR rs

Description:

The program unconditionally jumps to the address contained in general register rs, with a delay of one instruction.

Since instructions must be word-aligned, a Jump Register instruction must specify a target register (rs) whose two low-order bits are zero. If these low-order bits are not zero, an address exception will occur when the jump target instruction is subsequently fetched.

Operation:

Exceptions:

None

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