pipeline, which includes descriptions of the delay instructions (instructions that follow a branch or load instruction in the pipeline), interruptions to the pipeline flow caused by interlocks and exceptions, and R4400 implementation of an uncached store buffer.
The FPU pipeline is described in Chapter 6.
Chapter Contents
- 3.1 - CPU Pipeline Operation
-
- 3.2 - Branch Delay
-
- 3.3 - Load Delay
-
- 3.4 - Interlock and Exception Handling
-
- 3.5 - R4400 Processor Uncached Store Buffer
-
