A CPU Instruction Set Details



Format:

DSUBU rd, rs, rt

Description:

The contents of general register rt are subtracted from the contents of general register rs to form a result. The result is placed into general register rd.

The only difference between this instruction and the DSUB instruction is that DSUBU never traps on overflow. No integer overflow exception occurs under any circumstances.

This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.

Operation:

Exceptions:

Reserved instruction exception (R4000 in 32-bit mode)

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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