A CPU Instruction Set Details



Format:

DSRAV rd, rt, rs

Description:

The contents of general register rt are shifted right by the number of bits specified by the low-order six bits of general register rs, sign-extending the high-order bits. The result is placed in register rd.

This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.

Operation:

Exceptions:

Reserved instruction exception (R4000 in 32-bit mode)

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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