A CPU Instruction Set Details



Format:

DSLL rd, rt, sa

Description:

The contents of general register rt are shifted left by sa bits, inserting zeros into the low-order bits. The result is placed in register rd.

Operation:

Exceptions:

Reserved instruction exception (R4000 in 32-bit mode)

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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