A CPU Instruction Set Details



Format:

DADDI rt, rs, immediate

Description:

The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt.

An overflow exception occurs if carries out of bits 62 and 63 differ (2's complement overflow). The destination register rt is not modified when an integer overflow exception occurs.

This operation is only defined for the R4000 operating in 64-bit mode. Execution of this instruction in 32-bit mode causes a reserved instruction exception.

Operation:

Exceptions:

Integer overflow exception
Reserved instruction exception (R4000 in 32-bit mode)

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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