A CPU Instruction Set Details



Format:

BEQ rs, rt, offset

Description:

A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general register rt are compared. If the two registers are equal, then the program branches to the target address, with a delay of one instruction.

Operation:

Exceptions:

None

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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