A CPU Instruction Set Details



Format:

ADDU rd, rs, rt

Description:

The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. No overflow exception occurs under any circumstances. In 64-bit mode, the operands must be valid sign-extended, 32-bit values.

The only difference between this instruction and the ADD instruction is that ADDU never causes an overflow exception.

Operation:

Exceptions:

None

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

Generated with CERN WebMaker
statistics