A CPU Instruction Set Details



Format:

ADDIU rt, rs, immediate

Description:

The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt. No integer overflow exception occurs under any circumstances. In 64-bit mode, the operand must be valid sign-extended, 32-bit values.

The only difference between this instruction and the ADDI instruction is that ADDIU never causes an overflow exception.

Operation:

Exceptions:

None

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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